1. Field of the Invention
The invention disclosed herein relates generally to the device configuration and fabrication process of semiconductor switching devices. More particularly, this invention relates to a novel and improved device configuration and fabrication process for providing high frequency power switching devices.
2. Description of the Prior Art
As there is an ever growing demand for high frequency switch power devices, conventional device configurations and manufacturing processes of power switching devices are still limited by speed-limiting capacitance between the gate and drain of the power transistors, e.g., MOSFET and IGBT. There is an urgent need to overcome such limitations especially when high frequency switching power supplies are providing power to wide range of electronic devices.
Referring to FIGS. 1A to 1D for conventional techniques wherein FIGS. 1B and 1D show a reduction of the gate-drain capacitance for the typical planar and trenched DMOS cell of FIGS. 1A and 1C respectively. Specifically, a terrace gate dielectric layer that is thicker than regular gate oxide layer is formed under a terrace gate. The gate-drain capacitance is reduced because there is a thicker terrace gate oxide layer between the gate and the drain. For a trenched DMOS cell shown in FIG. 1D, similarly, a thicker gate oxide layer is formed at the bottom of the trench to reduce the gate-drain capacitance. However, such device configurations still have problems and limitations. One problem with the terrace gate-oxide design is that the process is not self-aligned; therefore it is hard to reduce the cell size. In carrying out the process of forming the terraced gate the terrace dielectric and gate electrode are subject to lithographic misalignment. The size of the device is increased due to a requirement to allow for misalignment tolerance between the terraced gate and the terrace dielectric layer. A second problem for this design is that the thick terrace dielectric layer reduces the accumulation of carrier in the drain area under the dielectric terrace and this increases the Rdson of the device. Furthermore, the reduction of Crss is limited by the thickness of the terrace dielectric. This is especially true for the thick trench bottom oxide approach in trench device where the thick bottom oxide is hard to make. The increase of oxide thickness in the trench bottom also reduces the accumulation of carriers in the drain region under the thick oxide hence increase the device on-resistance Rdson.
In another patented invention U.S. Pat. No. 5,894,150, Hshieh et al. disclose a split gate configuration to achieve a purpose of reducing the gate-drain capacitance. The gate of a DMOS cell is split into two segments as that shown in FIG. 1E. The split gate configuration reduces the gate-drain capacitance because it eliminates the contribution to the gate-drain capacitance from the gate-drain overlapping areas. It is clear that the split gate configuration disclosed by Hshieh does achieve gate-drain capacitance reductions. However, with the split gate configuration, there are still some fringing electric field couplings between the gate electrodes to the epitaxial layer connecting to the drain electrode. Further improvements are still required to eliminate the fringing capacitance resulted from such couplings between the gate and the drain.
Baliga disclosed in U.S. Pat. No. 5,998,833 another DMOS cell as that shown in FIG. 1F to reduce the gate-drain capacitance by placing the source electrode underneath a trenched gate. There are some shielding effects provided by the source electrode underneath the trenched gate. However, similar to a configuration as that shown in FIG. 1E, there are still fringing capacitance between the gate electrodes and the epitaxial layer connected to the drain electrode. Therefore, further improvements are still required to further reduce the gate-drain capacitance such that further improvements of high frequency switching performance can be achieved.
Therefore, a need still exists in the art to provide an improved device configuration and manufacturing methods to provide MOSFET device with further reduced gate-drain capacitance such that the above-discussed limitations as now encountered in the prior art can be resolved.